1. Field of the Invention
The present invention relates to a data memory system, and more specifically to a circuit for elevating reliability of a data memory system.
2. Description of Related Art
At present, a data memory is widely used in various office instruments, such as a word processor and a telecopier, and in various domestic instruments, such as a television receiver and an audio system, as a means for holding information such as a selected channel or frequency and a sound volume in the television receiver, which has to be maintained although an electric power is shut down.
Referring to FIG. 1, there is shown is a block diagram illustrating a construction of an EEPROM (electrically erasable programmable read only memory), which is a typical example of the conventional data memory system, and which is disclosed in NEC Data Sheet IC-6053 of NEC Corporation. As shown in FIG. 1, this typical conventional memory data system comprises a memory 1 including a plurality of memory locations 12, an I/O (input/output) buffer 9 coupled to an external bus 19 for interfacing to an external device, an address latch 7 coupled through a system bus 13 to the I/O buffer 9 for latching an address fetched through the I/O buffer 9, an address decoder 6 coupled through an address bus 15 to the address latch 7 and associated to the memory 1 for selecting a memory location designated by the address latched in the address latch 7, a data latch 8 coupled to the system bus 13 and also to the memory 1 through a data bus 14 for holding data read from or to be written to the selected memory location 12, an instruction decoder 10 coupled to the system bus 13 to receive an instruction given through the I/O buffer 9 from the external device for analyzing the given instructions and for controlling the address latch 7, the address decoder 6 and the data latch 8, and a write/read timing generator 11 for supplying a timing signal to the memory 11.
Thus, data supplied through the I/O buffer 9 from the external device is analyzed by the instruction decoder 10. If it is discriminated that the given data is an address, the given data, namely, the given address, is set to the address latch 7 under control of the instruction decoder 10. On the basis of the address latched in the address latch 7, the address decoder 6 selects one memory location within the memory 1. A data writing or reading is performed for the selected memory location by means of the data latch 8.
In general, the addresses to be read and written of the memory system are determined when an instrument incorporating therein the data memory system is designed, and thereafter, the addresses are never changed.
In the above mentioned conventional data memory system, therefore, if the address designated from the external device is the same, a read/write is performed on the same memory region. Therefore, the number of writings varies from one memory location to another. On the other hand, the lifetime of the entire data memory system is determined by the memory location having a maximum number of writings performed. Accordingly, memory regions having a small number of writings performed becomes wasteful. This is not efficient.